Assembling microLEDs into displays is challenging due to the need for precise placement of millions of tiny microLEDs. Fluidic self-assembly, laser transfer, and stamp transfer are all candidate technologies. Among these, elastomer stamp transfer has proven to be a scalable, high-yield solution. The advancements in mass transfer technology are now being applied to heterogeneous integration challenges beyond displays, enabling improved performance and flexibility in combining different types of components into complex electronic systems.

Chiplets are becoming key components: They not only help tackle the forces that are threatening to end Moore’s Law, they are also the crucial gateway technology for e.g. electro-optical systems, non-CMOS devices, and sensors, and they promise to sustain the race for high performance at low cost. Advanced packaging is key to the widespread acceptance of chiplets. With 30 years of experience in this field, Fraunhofer IZM plays a crucial role in the microelectronics community. The presentation will discuss the basics of chiplet integration and highlight their advantages over traditional monolithic chips. It addresses the challenges in terms of reliability and the associated design and development requirements and highlights the need to consider design optimization, material selection, test procedures, fault tolerance, and continuous improvement holistically and from the beginning. A combination of these is essential to make chiplet systems meaningfully more reliable.

The very fast innovation pace on AI processing hardware is pushing the semiconductor packaging industry to set up high volume production capability for ultra large very high-density interconnection interposers. This is creating a strong momentum for high density fan out Panel Level Packaging (PLP).

In the domain of electrification, there is a race to power density and efficiency. This is fueling the industry for designing and industrialize new ways to interconnect power chips with drivers and passives for low electrical losses, typically low RdsOn and low stray inductance.

Those two domains have very different requirements in terms of interconnect density and current capability, but they share the same technology trend with the integration of latest innovations from different interconnection manufacturing concepts:  PCB, high density substrate, wafer level packaging, embedded die and passives, and traditional packaging technology such copper pillar flip chip, die attach sintering.

This presentation gives an overview of the Panel Level Packaging technology trends for main semiconductor applications. Then it presents the experience and key challenges faced during the industrialization of an actual high volume PLP manufacturing line.

The chiplet era is upon our industry, driving exponentially increasing demand for die-to-die interconnect that is met with an expanding variety of package architectures. Interposers, hybrid bonding, and novel substrate technologies are approaching the scale of upper metals layers in a chip, driven by insatiable demand from artificial intelligence and high-performance computing applications. As electronic design automation tools catch up to these advancements, designers will completely blur the boundary between chip wires and package wires. Beyond these widely discussed applications, chiplets are coming for microcontrollers too, enabling the disaggregation of non-volatile memory, analog, and digital blocks. This talk will explore macro trends of the chiplet era and contemplate what path lies beyond – perhaps the monolithic decades will become a brief historical exception.

The world’s digitalization is driving an enormous increase in data generation, expected to reach nearly 500 zettabytes by 2030. This data deluge leads to a dramatic rise in energy consumption, which is unsustainable in the medium term. Technological breakthroughs must be developed to significantly improve (by a factor of 1000) the power efficiency of electronics. Today, it is clear that a single technology cannot meet all the requirements of the most demanding computing and connectivity ICs. It is thus evident that heterogeneous 3D integration or advanced packaging is the way forward to combine different technologies and also enable novel architectures (such as chiplets) that bring various functions closer together. This talk will detail the different technologies under development, such as hybrid bonding, TSV (Through-Silicon Vias), interposers, and wafer-to-wafer or die-to-wafer approaches. Recent results and demonstrators will also be presented.

In order to reduce the clearly visible trend of global warming, the changeover from fossil fuels to electrification is driven forward. Since transport largely contributes to C02 emissions the electrification of Plug-in Hybrid Electric Vehicles and Electric Vehicles is crucial. In this dynamic field power modules are needed that find the right balance between conflicting requirements like power density, scalability, design flexibility and performance. The challenge with modules in comparison to discretes is that part of the circuity is included in the module and that no standard is defined. In addition, due to the very different material and physical properties of wide band gap materials like SiC, learnings from the Si world can only be used to a limited extend. Emerging from the two different trends – frame based modules and molded modules – a concept combining the best of both and enabling 3D routing will be presented. The talk concludes with an outlook towards standardization due to the request for 2nd source capability.