Today, most of the package substrates for HPC driven by AI (artificial intelligence) are made by the 2.5D IC integration. In general, for 2.5D or CoWoS (chip on wafer on substrate), the SoC and high bandwidth memories (HBMs) are supported by a TSV-interposer and then solder bump and underfill on a build-up package substrate. However, because of the ever-increasing size of the TSV-interposer, the manufacture yield loss of the TSV-interposer is becoming unbearable. The key players such as NVIDIA, AMD, Intel, SK Hynix, Samsung, Micron, TSMC, etc. are working very hard to eliminate the TSV interposer and put the HBMs directly on top of the SoC (3.3D IC integration). Front-end integration of some of the chiplets (before package heterogeneous integration) can yield a smaller package size and a better performance (3.5D IC integration). In the past few years, 2.3D IC integration or CoWoS-R is getting lots of traction. The motivation is to replace the TSV-interposer with a fan out fine metal L/S redistribution-layer (RDL)-substrate (or organic-interposer). In general, for 2.3D, the package substrate structure (hybrid substrate) consists of a build-up package substrate, solder joints with underfill, and the organic-interposer. Today, 2.3D is already in production. Recently, TSMC published two papers on replacing the large-size TSV-interposer by LSIs (local silicon interconnects, i.e. Si bridges) and embedding the LSIs in fan-out RDL-substrate. TSMC called it CoWoS-L. Recently, since Intel’s announcement on the glass core substrate for their one-trillion transistors to be shipped before 2030, glass core substrate has been a very hot topic. Since the shipments of co-packaged optics (CPO) by Intel and Broadcom CPO have been getting lots of tractions. In this lecture, the introduction, recent advances, and trends in the substrates of 3.5D IC integration, 3.3D IC integration, 3D IC integration, 2.5D IC integration, 2.3D IC integration, 2.1D IC integration, 2D IC integration, fan-out RDL, embedded Si-bridge, CoWoS-R, CoWoS-L, CPO, and glass core for HPC driven by AI will be discussed. Some recommendations will be provided.

CONTENTS
• Introduction
• Substrate Definition
• Substrates for Chiplet and Heterogeneous Integration
• 2D IC Integration
• 2.1D IC Integration
• 2.3D IC Integration
• 2.5D IC Integration
• 3D IC Integration
• 3.3D IC Integration
• 3.5D IC Integration
• Bridges Embedded in Build-up Substrates
• Bridges Embedded in Fan-Out EMC with RDLs
• Glass-Core Build-up Substrates and TGV-Interposers
• CPO Substrates
• Summary and Recommendations

This course has a seminar-like approach, it is NOT aimed at people who already consider themselves as packaging experts.
The course is suitable for

• students, in material science or IC design, electronics, or microelectronics
• people collaborating with packaging engineers: such as marketing, sales, components test, IC design, application development, or device characterization .. So, everyone not so close to packaging technologies, but curious about them…

After a theorical presentation on the basics of packaging, covering the main steps, machines, physical and industrial critical points, you will have to apply these newly learnt notions in practice, by identifying suitable packaging solutions to meet a specific product requirement…
The purpose of this handmade packaging experiment is to gain a better understanding of the challenges faced by packaging engineers in their daily work, and to realize the fundamental role of microelectronics packaging in enabling an IC die to become the expected product.

Note : the practical exercise limits the course to 12 attendees

The modern car has increased semiconductor content and dollar value.  Semiconductors enable the majority of innovations in automotive.  During the vehicle’s use-life, electronics in the automotive underhood may be exposed to sustained high temperatures of 125-150°C for extended periods of time.  The Automotive Electronics Council (AEC) has graded electronics for automotive purposes into four categories: grade-0, grade-1, grade-2, and grade-3.  Grade-0 components have the most demanding criteria of the four grade categories, with predicted power temperature cycling ranging from -40°C to +150°C for 1000 cycles and ambient temperature cycling ranging from -55°C to +150°C for 2000 cycles.  Furthermore, the grade-0 components are expected to be capable of sustaining high-temperature storage for 1000 hours at 175°C.  With the introduction of new packaging architectures, packaging applications have continued to evolve, allowing for powerful computing on mobile automobile platforms.  New materials and integration technologies have also emerged, allowing for tighter integration of electronics, sensing, and processing into the structural characteristics of the vehicle.  The automobile platform faces a series of constraints particular to the real-time context for enabling sophisticated functionality.

Specifically, the course will encompass the following topics:

1. Role of electronics on the automotive platform
2. Automotive environments
3. Advanced Packaging Interfaces
4. Vibration Effects
5. Sustained High Temperature and Wide Thermal Extremes
6. Corrosion Propensity
7. Accelerated Testing
8. Prognostic Health Management
9. Virtual Qualification and Simulation Driven Co-Design

Who Should Attend:

The goal of the course is to provide the students a comprehensive understanding of the materials and reliability consideration in the design of electronics for operation in the automotive platform.  The course is intended to have an intermediate degree of difficulty to serve as an introduction for engineers and managers looking to design electronics for operation in the automotive underhood.

The recent development of silicon photonics and the opportunities it represents for addressing a number of challenges in the fields of HPC/AI, datacom and sensors have accelerated the convergence of electronic and photonic components. This combination of both technologies cannot be achieved without recourse to advanced packaging. Here, we review the challenges and technologies enabling this paradigm shift, focusing on the underlying physics and the expected developments.

This short course will deal with the following topics:
– Silicon Photonics: basics on devices , modules and applications
– Evolving needs in data transmission, Ethernet switches roadmap
– A short story of early Electronic/Photonics integration
– Co-packaging optics : the challenges
– 3D packaging building blocks
– The coupling challenge
– Recent demonstations of CPO integration
– Outlook, photonics interposers

Substrate and interposer technologies play a significant role in the cost, performance and reliability of electronic packages, components and systems. In this PDC, the fundamentals, and advanced packaging applications of organic, ceramic, silicon and glass substrate technologies as well as interposers will be presented and extensively discussed.

The PDC is structured into two three main sections, namely, a) applications driving advanced packaging and heterogeneous integration, b) advanced substrates technologies and c) interposer technologies.

In the first section, emerging applications that drive innovations in advanced packaging substrates and interposer technologies will be presented. This includes applications in the fields of wireless communication, radar sensing, high performance computing (HPC) and AI in a wide range of industries.

The second section will commence with an in-depth examination of advanced substrate technologies, materials and processes, including high-density organic laminates, glass and silicon substrates. Recent breakthroughs in substrate fabrication processes, including advanced lithography, laser drilling, and metallization techniques will be highlighted. Attendees will gain practical insights into overcoming common challenges like warpage control, fine-pitch routing, and multilayer RDL, ensuring reliability and manufacturability in next-generation electronic packages. Furthermore, methods for measuring the relative dielectric constant (Dk) and loss tangent (Df) of substrate materials from 1 GHz to over 100 GHz will be presented and demonstrated for a wide range of substrates, including organic laminates, thin-film RDL polymers, mold, glass, silicon and Ajinomoto Build-Up Films (ABF).

Recent developments in silicon, glass and organic-based interposer technologies will be presented in the last section of the PDC. The application of interposers for the development of chiplets, especially for HPC and AI applications, will be extensively discussed. Die-to-die (D2D) interconnects for chiplets, and UCIe (Universal Chiplet Interconnect Express) specifications will also presented. Participants will learn more about the integration of 2.5D and 3D packaging solutions, and the role of interposers in enabling heterogeneous integration. The pros and cons of silicon, glass and organic interposers will also be discussed.

Finally, guidelines for selecting substrate and interposer technologies as well as materials and processes for application-specific advanced packaging and heterogeneous integration will be given.

Outline

1. Applications driving innovations in advanced packaging and heterogeneous integration
2. Fundamentals of advanced substrate technologies, materials and processes, including high-density organic laminates, glass and silicon substrates
3. Measured Dk and Df values of substrate materials from 1 GHz to over 100 GHz
4. Fundamentals of silicon, glass and organic-based interposer technologies
5. Pros and cons of silicon, glass and organic interposers
6. Chiplets, die-to-die (D2D) interconnects and UCIe
7. Guidelines for selecting substrate and interposer technologies for application-specific advanced packaging and heterogeneous integration

Wafer and Panel Level Packaging are two of the dominating trends in microelectronics packaging. Both approaches with different flavors as RDL last face-up or face-down have reached maturity and are introduced in high volume manufacturing. Main driver for moving from wafer to panel level packaging is of course lowering the packaging cost. More packages can be processed in parallel and panel formats have a much better area utilization (ratio between panel/wafer size and package size) than round wafer shapes. With the advent of chiplet technology and the application to large body size packages e.g. HPC modules Panel Level Packaging is actually gaining momentum as an option for lower cost and high-density packaging. The PDC will give a status of the current Fan-in and Fan-out Wafer Level Packaging as well as Panel Level Packaging. This will include material and process discussion, technologies, equipment, applications and market trends as well as cost and environmental aspects.

 The PDC will give a status of the current Fan-in and Fan-out Wafer Level Packaging as well as Panel Level Packaging. This will include material and process discussion, technologies, equipment, applications and market trends as well as cost and environmental aspects.

Outline

1. Introduction to Advanced Packaging
2. Trends in Wafer Level Packaging
3. Fan-In and Fan-out on Wafer Level: Material, Processes, Applications
4. Introduction and Definition Panel Level Packaging
5. Fan-out Panel Level Packaging: Technologies, Challenges and Opportunities
6. Cost & Environment Modelling

Who Should Attend

Anyone who is interested in Advanced Packaging, Fan-in and Fan-out Wafer Level Packaging and the transition to Panel Level Packaging. Engineers and manages are welcome as detailed technology descriptions as well as market trends, applications and cost modelling are presented.