Today, most of the package substrates for HPC driven by AI (artificial intelligence) are made by the 2.5D IC integration. In general, for 2.5D or CoWoS (chip on wafer on substrate), the SoC and high bandwidth memories (HBMs) are supported by a TSV-interposer and then solder bump and underfill on a build-up package substrate. However, because of the ever-increasing size of the TSV-interposer, the manufacture yield loss of the TSV-interposer is becoming unbearable. The key players such as NVIDIA, AMD, Intel, SK Hynix, Samsung, Micron, TSMC, etc. are working very hard to eliminate the TSV interposer and put the HBMs directly on top of the SoC (3.3D IC integration). Front-end integration of some of the chiplets (before package heterogeneous integration) can yield a smaller package size and a better performance (3.5D IC integration). In the past few years, 2.3D IC integration or CoWoS-R is getting lots of traction. The motivation is to replace the TSV-interposer with a fan out fine metal L/S redistribution-layer (RDL)-substrate (or organic-interposer). In general, for 2.3D, the package substrate structure (hybrid substrate) consists of a build-up package substrate, solder joints with underfill, and the organic-interposer. Today, 2.3D is already in production. Recently, TSMC published two papers on replacing the large-size TSV-interposer by LSIs (local silicon interconnects, i.e. Si bridges) and embedding the LSIs in fan-out RDL-substrate. TSMC called it CoWoS-L. Recently, since Intel’s announcement on the glass core substrate for their one-trillion transistors to be shipped before 2030, glass core substrate has been a very hot topic. Since the shipments of co-packaged optics (CPO) by Intel and Broadcom CPO have been getting lots of tractions. In this lecture, the introduction, recent advances, and trends in the substrates of 3.5D IC integration, 3.3D IC integration, 3D IC integration, 2.5D IC integration, 2.3D IC integration, 2.1D IC integration, 2D IC integration, fan-out RDL, embedded Si-bridge, CoWoS-R, CoWoS-L, CPO, and glass core for HPC driven by AI will be discussed. Some recommendations will be provided.

CONTENTS
• Introduction
• Substrate Definition
• Substrates for Chiplet and Heterogeneous Integration
• 2D IC Integration
• 2.1D IC Integration
• 2.3D IC Integration
• 2.5D IC Integration
• 3D IC Integration
• 3.3D IC Integration
• 3.5D IC Integration
• Bridges Embedded in Build-up Substrates
• Bridges Embedded in Fan-Out EMC with RDLs
• Glass-Core Build-up Substrates and TGV-Interposers
• CPO Substrates
• Summary and Recommendations

The recent development of silicon photonics and the opportunities it represents for addressing a number of challenges in the fields of HPC/AI, datacom and sensors have accelerated the convergence of electronic and photonic components. This combination of both technologies cannot be achieved without recourse to advanced packaging. Here, we review the challenges and technologies enabling this paradigm shift, focusing on the underlying physics and the expected developments.

This short course will deal with the following topics:
– Silicon Photonics: basics on devices , modules and applications
– Evolving needs in data transmission, Ethernet switches roadmap
– A short story of early Electronic/Photonics integration
– Co-packaging optics : the challenges
– 3D packaging building blocks
– The coupling challenge
– Recent demonstations of CPO integration
– Outlook, photonics interposers